The present invention relates to a buffer circuit, and more precisely to a buffer circuit provided in a semiconductor memory device.
In general, a buffer is provided in the semiconductor memory device for the purpose of making a precise signal interface between an internal portion and an external portion of the semiconductor memory device. Further, if the semiconductor memory device interfaces the signal under conditions that are different from the conditions of the external portion, the buffer is responsible for mitigating the impacts caused by the differing conditions.
FIG. 1 shows a conventional buffer that is formed with a current mirror type differential amplifying structure that compares an input signal IN to the level of a predetermined reference voltage VREF and that outputs the compared results as an output signal OUT.
More specifically, the conventional buffer includes a differential amplifying unit 10 that compares a potential difference between the input signal IN and a bias signal BIAS and outputs it as the output signal OUT, a bias supply unit 12 that is driven by a reference voltage VREF so as to provide the bias signal BIAS to the differential amplifying unit 10, and a load 14 that provides the same pull-down current to a common node of the differential amplifying unit 10 and the bias supply unit 20.
In the conventional buffer, if the input signal IN is input at a level that is relatively higher than the level of the reference voltage VREF, the potential of node O_ND1 descends to allow the output signal OUT to be output at a high level, whereas if the input signal IN is input at a level that is relatively lower than the level of the reference voltage VREF, the potential of the node O_ND1 ascends to allow the output signal OUT to be output at a low level.
A plurality of buffers is provided, each corresponding to a pad of the semiconductor memory device, and multiple buffers having the properties mentioned above are included in the plurality of buffers.
However, since the buffers are provided for each pad of the semiconductor memory device, a problem occurs in that the size of the memory chip increases due to the number of the buffers. Additionally, a circuit (i.e., a reference voltage generating circuit) that controls the buffer is needed for each of the respective buffers, thus further increasing the size of the memory chip.